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[Other resource] cpld_bus

Description: CPLD的VerilogHDL总线代码,在EPM7128SLC84-10+Quartus4平台上运行通过.-CPLD bus Verilog HDL code, the PLD-10 Quartus4 platform to run through.
Platform: | Size: 218582 | Author: hamlemon | Hits:

[Other resource] RISC8.ZIP

Description: 简单的一个8位RISC，Verilog HDL代码,类型为pic16c57-a simple eight RISC, Verilog HDL code, the type of pic16c57
Platform: | Size: 81595 | Author: 陈正一 | Hits:

[Other resource] systemcTOVerlogHDL

Description: 一个带波形输出的扫频模板systemC源程序， 该程序在SystemCStudio开发平台下生成， 实现systemC仿真、波形显示以及自动生成Verilog HDL代码。-waveform output with a sweep of the template systemC source, SystemCStudio the program development platform in the next generation, realize systemC simulation, waveform display and automatically generate Verilog HDL code.
Platform: | Size: 461020 | Author: 李义 | Hits:

[Internet-Network] iicreciver

Description: iic slave verilog hdl code
Platform: | Size: 1590 | Author: hrui | Hits:

[VHDL-FPGA-Verilog] source9-10

Description: verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，9-10章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code, 9-10
Platform: | Size: 15360 | Author: 余月森 | Hits:

[VHDL-FPGA-Verilog] source11-12

Description: verilog hdl教程135例:verilog hdl语言类似于C语言，便于学习。本文档带有源代码，11-12章-Verilog HDL 135 cases Guide : Verilog HDL language similar to the C language, to facilitate learning. This document with the source code 11-10-12 Cap
Platform: | Size: 9216 | Author: 余月森 | Hits:

[VHDL-FPGA-Verilog] risc_cpu

Description: 这是一个Verilog HDL编写的RISC cpu的程序，该程序共10个子程序，实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。-This is the RISC cpu code which writed by Verilog HDL.This code has ten subprogram which came true the simple RISC cpu. Beginner can reference this example to study the Hardware discription language and the design manner. This program have passed the Modelsim validate.
Platform: | Size: 44032 | Author: 施向东 | Hits:

[VHDL-FPGA-Verilog] 20060412183015974

Description: 是关于dct的Verilog HDL源代码和测试程序-on the Verilog HDL source code and testing procedures
Platform: | Size: 30720 | Author: 凌风 | Hits:

[Other Embeded program] yunsuan-verilog

Description: 运算器的实现，即实验指导书中的实验一，文件中包含有原代码及端口设置（可变），用vrilog HDL编程，Xilinx ISE 6仿真，并在实际电路中得到实现．-operations for the realization of the experimental guidance of a book. document contains the original code and port settings (variable), with vrilog HDL programming, Xilinx ISE 6 simulation, and the actual circuit realization.
Platform: | Size: 1600512 | Author: 王越 | Hits:

[Other Embeded program] FPGA_test_frequency

Description: 本原码是基于Verilog HDL语言的FPGA原程序，主要用于测频率，特点主要是可以更快地测频。实时性更高。-primitive code is based on Verilog HDL FPGA original program, mainly for the measurement frequency, the main features can be faster frequency measurement. Real-time higher.
Platform: | Size: 1024 | Author: jevidyang | Hits:

[VHDL-FPGA-Verilog] URAT-code

Description: 使用Verilog HDL语言编写的URAT接口代码，实现串行数据传输功能-UART of Verilog HDL code to realize serial communication functio by Simon of Shenzhen University.
Platform: | Size: 1024 | Author: Simon | Hits:

[VHDL-FPGA-Verilog] CD-ROM-code-(verilog-hdl)

Description: 数字信号处理的fpga实现 第2版-光盘源码（verilog HDL）-Fpga implementation of digital signal processing 2nd Edition- CD source (verilog HDL)
Platform: | Size: 356352 | Author: 周诚 | Hits:

[VHDL-FPGA-Verilog] flowing-water-light-code

Description: 这是一段基于DE2开发板的流水灯Verilog hdl 代码-This is a based on DE2 development board of flowing water light Verilog HDL code
Platform: | Size: 11264 | Author: sishen | Hits:

[Industry research] Verilog-HDL-Code-Examples

Description: various verilog code ezamples for brginners.good point to start with.
Platform: | Size: 51200 | Author: asad | Hits:

[VHDL-FPGA-Verilog] Verilog HDL program

Description: 文件详细讲述了使用XILINX产FPGA在ISE平台开发的方法，介绍了Modelsim，chipscope,textbench等仿真方法，并含大量实例以及源代码(File details on the use of XILINX produced FPGA in the ISE platform development methods, introduced the Modelsim, chipscope, textbench and other simulation methods, and contains a large number of examples, as well as source code)
Platform: | Size: 11567104 | Author: 没伞的孩子 | Hits:

[VHDL-FPGA-Verilog] 数字信号处理的FPGA实现-第三版-verilog源程序

Description: 数字信号处理的FPGA实现, 包括了FPGA基础知识，浮点运算，信号处理的FIR FFT等，附录包含源代码(Digital signal processing FPGA implementation, including the basic knowledge of FPGA, floating point operations, signal processing FIR, FFT, etc., the appendix contains the source code)
Platform: | Size: 4568064 | Author: btty | Hits:

[VHDL-FPGA-Verilog] signed_add

Description: 有符号定点数加法运算代码，使用Verilog HDL语言实现(Code writing in Verilog HDL,to solve the problem about signed number calculation.)
Platform: | Size: 2048 | Author: zhangchaoruo | Hits:

[VHDL-FPGA-Verilog] Assignment-2.3.tar

Description: HDL code using verilog
Platform: | Size: 19456 | Author: guy03 | Hits:

[VHDL-FPGA-Verilog] aes128-hdl-master

Description: Verilog AES hdl key 128 bit code and decode
Platform: | Size: 856064 | Author: Nguyen Nam | Hits:

[matlab] CICFilter

Description: 一个CIC滤波器的源代码，基于verilog HDL语言(The source code of a CIC filter is based on Verilog HDL language.)
Platform: | Size: 4096 | Author: IT熊出没 | Hits:
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